A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

ITC : 2012 IEEE International Test Conference , 5-8 Nov. 2012 , Anaheim, CA, USAIn return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency

Acceleration of Seed Ordering and Selection For High Quality VLSI Delay Test

Seed ordering and selection is a key technique to provide high-test quality with limited resources in Built-In Self Test (BIST) environment. We present a hard-to-detect delay fault selection method to optimize the computation time in seed ordering and selection processes. This selection method can be used to select faults for test generation when it is impractical to target all delay faults resulting large test pattern count and long Computation time. Three types of selection categories are considered, ranged in the number of seeds it produced, which is useful when we consider computing resources, such as memory and storage. We also evaluate the impact of the selection method in mixed-mode BIST when seed are expanded to more patterns, and evaluate the statistical delay quality level (SDQL) with the original work. Experimental results show that our proposed method can significantly reduce computation time while slightly sacrificing test quality

Case of three delayed complications of radiotherapy: Bilateral vocal cord immobility, esophageal obstruction and ruptured pseudoaneurysm of carotid artery

金沢大学医薬保健研究域医学系We report the first case of three delayed complications following irradiation for laryngeal carcinoma: bilateral vocal cord immobility, obstruction of esophagus and spontaneously ruptured pseudoaneurysm of common carotid artery. Medial fixation of bilateral vocal cords and stenosis of cervical esophagus were noted at 28 years after radiotherapy. Spontaneous rupture of a pseudoaneurysm bulging into the hypopharynx and obstruction of the esophagus occurred at 35 years after irradiation. The life-threatening hemorrhage was successfully treated by microcoil embolization of the common carotid artery. The relationship between these complications and irradiation is also discussed. © 2008 Elsevier Ireland Ltd. All rights reserved

DART: Dependable VLSI Test Architecture and Its Implementation

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.2012 IEEE International Test Conference, 5-8 November 2012, Anaheim, CA, US

Design for consecutive transparency of RTL circuits

This paper presents a design-for-consecutive-transparency method that makes a core (RTL circuit) consecutively transparent using integer linear program-ming. Consecutive transparency of a core guarantees consecutive propagation of arbitrary test/response se-quences from the core inputs to the core outputs with some latency. Therefore, it is possible to apply/observe arbitrary test/response sequences to/from an embedded core consecutively at the speed of system clock by using interconnects and consecutively transparent cores in an SoC. Experimental results show that the proposed method introduces lower area overhead compared to the bypass method that adds direct paths from PIs to POs with multiplexers.http://library.naist.jp/mylimedio/dllimedio/show.cgi?bookid=100033931&oldid=6120

A DFT method for core-based systems-on-a-chip based on consecutive testability

This paper proposes a new methodology for testing a core-based systems-on-a-chip (SoC) based on a new concept of testability called consecutive testability. In the proposed method, test sequence of a core embedded deep in the design is propagated to the core inputs from the SoC inputs consecutively at normal system clock. Similarly response sequence is propagated to the SoC outputs from the core outputs consecutively at normal system clock. The propagation of test sequences and response sequences is achieved by using the consecutive transparency properties of surrounding cores and interconnections between cores. A design for testability (DFT) method for the consecutive testability is also proposed. The proposed method can test interconnections between cores thoroughly. Moreover, the method can test not only logic faults such as stuck-at faults, but also timing faults such as delay faults that require consecutive application of test patterns at speed of system clock.http://library.naist.jp/mylimedio/dllimedio/show.cgi?bookid=100028859&oldid=3225

An ILP formulation for consecutive testability of system-on-a-chip

This paper introduces a new concept called consecutive testability and proposes a design-for-testability method that makes a given SoC consecutively testable using integer lin-ear programming (ILP). A consecutively testable SoC can achieve consecutive application of arbitrary test sequence at the speed of system clock. The advantage is that it is pos-sible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of the system clock.http://library.naist.jp/mylimedio/dllimedio/show.cgi?bookid=100032622&oldid=5864